Tutorials

Abstract: This tutorial session will feature case studies that highlight the utility of topology optimization techniques in additively manufactured (AM) cooling solutions. The speakers will share basic optimization algorithms for passively and actively cooled heat sinks fabricated with AM. Finally, recent case studies will be used to highlight current progress and future trends in topology optimization. A corresponding discussion on the particular benefits of additive manufacturing for electronics cooling will take place at the end of the tutorial session.

Nenad Miljkovic
UIUC
Organizer & Moderator

Ron Warzoha
US Naval Academy
Organizer

Casper Andreasen
Technical University of Denmark
Presenter

Joe Alexandersen
University of Southern Denmark
Presenter

Biographies

Joe Alexandersen is an Assistant Professor at the University of Southern Denmark, Department of Mechanical and Electrical Engineering. He received his M.Sc. (2013) and Ph.D. (2016) degrees from the Technical University of Denmark. His research area is multiphysics simulation and optimisation, focused mainly on flow-based and heat transfer problems. His work has been internationally recognised by being awarded the 2015 ISSMO/Springer Prize for Young Scientists and the 2017 DTU Young Researcher Award.

Casper Schousboe Andreasen is an Associate Professor at the Technical University of Denmark, Department of Mechanical Engineering. He obtained his MSc (2008) and PhD (2011) from the same University with Professor Ole Sigmund as supervisor. His research interests are diverse covering both simulation of fluid flows, conjugate heat transfer, particle transport processes and tribology as well as the integration of the multiple physics in order to conduct topology and shape optimization. Currently he is scientific lead on a project named “Easy-E - Easy Energy Efficiency made Industry Available via Thermal Topology Optimisation” with industrial partners in the Danish industry.

Abstract: The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions, in a post-Moore world. The primary objective is to stimulate pre-competitive global collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. The HIR is sponsored by three IEEE Societies (Electronics Packaging Society, Electron Devices Society & Photonics Society) together with SEMI and ASME EPPD.

Session I of this HIR Tutorial will dealt with the near-term as well as far-term reliability challenges and needs faced by the six major application segments identified in the HIR Roadmap. These include: (i) Aerospace and Defense; (ii) Automotive; (iii) High Performance Computing and Data Centers; (iv) Medical, Health and Wearables; (v) Mobile; (Vi) IoT. The second Session (presented by Prof. Dasgupta) will present the phased vision and activities that are being formulated and proposed by the Reliability Technology Working Group in the HIR Team, as the pan-industry global approach needed to meet these reliability needs of the relevant stakeholders. This vision will be presented in terms of goals and milestones for the short-horizon (1-5 years); mid-horizon (5—10 years) and far-horizon (10-15 years) time-scales. The purposes for this HIR tutorial are to elicit audience interest, solicit voluntary participation from the community in the HIR activities & to stimulate collaboration among HIR stakeholders around the world.

Jin Yang
Intel
Organizer & Moderator

SB Park
The State University of New York (SUNY) at Binghamton
Presenter

Abhijit Dasgupta
University of Maryland
Presenter

Biographies

Prof. Seungbae (SB) Park is a Professor of Mechanical engineering of the State University of New York at Binghamton. He is also the director of Integrated Electronics Engineering Center (IEEC), a New York State Center for Advanced Technology (CAT).

He received his Ph.D. at Purdue University in 1994. Upon graduation, Dr. Park began his professional career at IBM. He was responsible for the reliability of IBM’s corporate flip chip technology in both leaded and lead-free solders and high performance packaging. Dr. SB Park started his academic career as a professor of mechanical engineering at the State University of New York at Binghamton in 2002.

Professor Park is an expert in Modeling and Simulation for electronics components and systems integration. His contribution s have been recognized many international awards and citations. He has contributed in various 2.5D/3D package development, MEMS packaging, reliability assessment of assemblies and systems, and smart electronics manufacturing. He has more than 200 technical publications and holds 4 US patents. Dr. Park served for several technical committees including a member of JEDEC 14-1 Reliability Committee, co-chair of iNEMI Modeling and Simulation TWG, chair of "Electronics Packaging" council in Society of Experimental Mechanics, and an associate editor for ASME Journal of Electronic Packaging. Professor Park has been helping consumer electronics and packaging companies such as Microsoft, Samsung, ASE, Xilinx, and Qualcomm, as a consultant.

Abhijit Dasgupta is Jeong H. Kim Professor of Mechanical Engineering at the University of Maryland (UMD), with research experience in the microscale and nanoscale mechanics and reliability physics of engineered materials used in conventional and additively manufactured 3D flexible electronic packaging and intelligent microsystems. He holds a Ph.D. in Theoretical and Applied Mechanics from the University of Illinois at Urbana-Champaign (UIUC), and has been a principal investigator at the Center for Advanced Life Cycle Engineering (CALCE) at UMD for over 30 years, conducting research in reliability physics, design for reliability, accelerated stress testing, and real-time health management. He has published over 300 articles and conference papers; served on editorial boards of three international archival journals; presented over 45 workshops and short courses; helped form research and educational roadmaps for the electronics industry, and provided consulting services to numerous industry leaders. He has presented numerous keynote talks at international conferences, received 6 best-paper awards and received 8 major awards in recognition of his research and educational contributions. He is an ASME Fellow, past Chair of the ASME Electronic and Photonic Packaging Division (EPPD), past member of the ASME Design, Manufacturing and Materials Segment Leadership Team (DMM-SLT) and Current Chair of Reliability Technology Working Group in the Heterogeneous Integration Roadmap (HIR) Team sponsored by IEEE/ASME/SEMI/IEPS/EDS.

Abstract: This tutorial will teach engineers how to design thermal systems using vapor chambers. A vapor chamber is also known as a 2D heat pipe; it is becoming a common component used to enhance thermal management. The annual shipments of vapor chambers for smartphones and laptops will reach over 100M units per year soon. Driven by such an application, vapor chambers become thin, light and low-cost alternatives to heat pipes and graphite and metal heat spreaders. However, most of thermal engineers do not know how to design their thermal systems using vapor chambers. For example, a vapor chamber’s performance can drop from 6,000 W/mK to 1,000 W/mK if its next cooling level is not arranged properly. In another case, a vapor chamber’s mass can increase from 30 to 90 grams if the specifications are not defined correctly. This tutorial will review different features offered by current and future vapor chambers with our thermal ground planes (TGPs) as examples. These features are temperature uniformity, maximum power, thickness, size, flexibility, bendability, foldability, RF transparency, heat flux, and cost. In addition, we will illustrate several cases to gain an insight into a thermal design using vapor chambers for smartphones, laptops, high performance computing (HPC), power electronics, and other applications.

Y. C. Lee
Kelvin Thermal
Organizer & Presenter

Ryan J. Lewis
Kelvin Thermal
Presenter

Biographies

Ryan J. Lewis is the Director of R&D in Kelvin Thermal. He is the lead inventor of major patents awarded to Kelvin Thermal for flexible thermal ground planes (TGPs). One of his notable accomplishments is the demonstration of the world’s thinnest vapor chamber with a thickness of only 0.15mm in 2018. In addition, he demonstrated a feasible polymer TGP in 2015, which was further enhanced in 2020. In 2021, Dr. Lewis' team developed a high power TGP good for over 1,000 Watts and another novel foldable TGP proven reliable over 150,000 folding cycles with a bending radius of 3mm. Dr. Lewis has designed over 20 different TGPs for customers.

Y. C. Lee is the President and CEO of Kelvin Thermal. Dr. Lee is recognized as a world leader in thermal management, packaging and interconnect technologies for microsystems integrating microelectronic, optoelectronic, microwave, microelectromechanical and nanoelectromechanical devices. He is an Emeritus Professor of Mechanical Engineering at the University of Colorado (CU) Boulder. At CU, he was the S. J. Archuleta Professor from 2011 to 2020 and the Director of DARPA Center on Nanoscale Science and Technology for Integrated Micro/Nano-Electromechanical Transducers (iMINT) from 2006 to 2012. Dr. Lee received the ASME InterPACK Achievement Award in 2013. He was the Editor of ASME Journal of Electronic Packaging from 2015 to 2020.

Abstract: The tutorial addresses the causes of thermal stress failures an electronic and photonic packaging and the ways they could be predicted and possibly prevented. The emphasis is on the physics of failure, the roles of the predictive modeling (both analytical and FEA) and accelerated testing.

Here are the main topics addressed: Physics of Thermal Stress; Thermal Stress Types in Adhesively Bonded or Soldered Assemblies; Typical Thermal Stress Failures and What Could Be Done to Reduce the Thermal Stress; Soldered Assemblies with Low Yield Stress Bonding Layer; Global and Local Thermal Stresses and Their Interaction; Tri-Material Assemblies; Flip-Chip Solder Joint Assemblies and the Role of the Underfill; Assemblies with Low Modulus Bonding Material at the Assembly Ends; Accelerated Testing of Assemblies Experiencing Thermal Loading; Failure Oriented Accelerated Testing (FOAT) vs.Highly Accelerated Life Testing(HALT); Elevated Stand-Off Heights Could Relieve Thermal Stress in Solder Joints: Column-Grid-Array (CGA) vs. Ball-Grid-Array (BGA) Design; Thermal Stress in Thin Films; Thermal and Lattice Mismatch Stresses; Thermal Stress Induced Bow (Warpage) and Bow -Free Assemblies; In-homogeneously Bonded Assemblies: Could Inelastic Strain in Them be Avoided?; Thermal Stress in Optical Fibers; Some Other Thermal Stress Related Problems in Electronic and Photonic Packaging.

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Ephraim Suhir
Portland State University
Organizer & Presenter

Ephraim Suhir is on the faculty of the Portland State University, Portland, OR, USA, Technical University, Vienna, Austria and James Cook University, Queensland, Australia, is CEO of a SBIR ERS Co. in Los Altos, CA, USA, Foreign Full Member of the National Academy of Engineering, Ukraine (he was born in that country);Life Fellow of the ASME, IEEE, SPIE, and the IMAPS; Fellow of the American Physical Society (APS), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE); and Associate Fellow of the AIAA. Ephraim has authored and co-authored about 500 publications, presented numerous keynote and invited talks worldwide, and received many professional awards, including 1992 ASME Clock Award, 1996 Bell Labs Dist. Member of Technical Staff Award, 1997 ASME InterPACK'97 General Chair Award, 1999 ASME Charles Russ Richards Memorial Award, and 2004 ASME Worcester Read Warner Medal. He is the third “Russian American”, after S. Timoshenko and I. Sikorsky, who received this prestigious award. His most recent awards are 2019 IEEE EPS Field Award and 2019 IMAPS Lifetime Achievement award.

Abstract: Wide-bandgap devices have pushed the operational limit of semiconductor devices in automotive power electronics packages to higher temperatures (>200°C). While a higher efficiency can be achieved through the use of wide-bandgap devices, the entire package must be re-designed with components that can withstand the higher temperature limits. Sintered silver and transient liquid phase bonds are potential candidates as bonded materials for use in higher temperatures however, the underlying mechanics of deformation under thermal loads and the resulting failure mechanisms in these materials are not well understood. Accelerated experiments conducted at NREL reveal that high-lead solder joints have better reliability than sintered silver under extreme thermal cycling conditions. Furthermore, efforts to develop a crack propagation model for the high-temperature materials are described.

Paul Paret
National Renewable Energy Laboratory
Organizer & Presenter

Paul Paret is a researcher in the Center for Integrated Mobility Sciences at the National Renewable Energy Laboratory. In this role, Paul leads the computational modeling efforts to simulate the thermal and thermomechanical behavior and develop lifetime prediction models of various bonded materials in power electronics packages used in electric-drive vehicles and aviation systems. He conducts design optimization studies to identify the optimal component layers and geometry within power electronics package topologies to improve their power density, efficiency, and reliability. Additionally, he performs mechanical characterization and reliability evaluation experiments to identify the fundamental failure mechanisms of materials under harsh operating conditions. Paul has published several articles including journals, conference papers, technical reports, and a book chapter on the thermomechanical performance and lifetime prediction models of power electronics materials. Paul has a master's degree in Aerospace Engineering Sciences from the University of Colorado, Boulder and a bachelor's degree in Mechanical Engineering from College of Engineering, Trivandrum, India.