Matthew Walsh
Industrial Base Analysis and Sustainment (IBAS)
Naval Surface Warfare Center
Crane, IN
Presentation Title: OUSD IBAS RESHAPE Project
Abstract: As microelectronic technology developments occurred in the 1980s and 1990s, it was perceived that packaging technologies became very mature and did not require new developments. Therefore, the majority of microelectronics packaging manufacturing was off shored to China and Pacific Rim countries such as Singapore, Malesia, Taiwan, Hong Kong, Indonesia for their low-cost labor and the absence of environmental restrictions to manufacturing. The microelectronics packaging industry since this off-shoring has remained being seen as mature with no requirements for developments and thus remains off-shore.
With Moore's Law coming to an end for IC processing, and a continuing need to reduce SWaP-C and increase performance, the introduction of 2.5-D and 3-D Advanced Packaging has become a focal point for DoD and Commercial applications. It is now in the forefront of development activities worldwide. As the microelectronics evolution progresses, circuit feature sizes decrease to accommodate the need for high-density packaging.
Theoretical feature size limits in the 2-D space and the cost to increase wafer size forces suppliers to move towards 3-D heterogeneous architectures. Integrating ICs from multiple technology nodes to increase cost-efficiency by only fabricating the components that need the highest performance, power advantage, and area savings in the latest node technology, while fabricating other system components at cheaper nodes. Improvements in advanced packaging is required for seamless integration. Although the European and Asian semiconductor industries have embraced these developments, no single country has emerged as a front-runner in the development and scale-up of advanced microelectronics 3-D packaging technologies and manufacturing processes. This provides an opportunity for the US to advance as a worldwide leader, developer, and supplier of these foundational and dual-use technologies.
The focus of the OUSD IBAS RESHAPE (Re-shore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics) effort is to develop a domestic, trusted, pure-play and open-access advanced packaging manufacturing ecosystem for low-volume/high-mix production of 2.5-D and 3-D Advanced System Integration and Packaging (ASIP) secure solutions. This prototype effort relates to foundational Advanced Packaging manufacturing capabilities required for advanced system integration of microelectronics packages including the following:
- Wafer Preparation
- Wafer Bumping
- Silicon Interposer Fabrication
- III/V Interposer Fabrication
- Classified Interposer Assembly
- Advanced Test and Failure Analysis Capability
- Fan-Out Wafer-Level Packaging
- Wafer-Level High-Density Interconnects
- Advanced Thermal Technologies
- Specialized Packaging for RF and Photonics
- Assembly Design Kits (ADKs) for SOTA Computer-Aided Design (CAD) Tools
Biography: Matthew Walsh is the Advanced Packaging Chief Engineer, Industrial Policy, Industrial Base Analysis and Sustainment (IBAS) Program Office of the Assistant Secretary of Defense for Industrial Base Policy. He is the technical lead on the Secure Advanced Packaging project within the Reshore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics (RESHAPE) effort, and technical SME for other microelectronics projects within the OSD IBAS. Within the Navy, Matt was Advanced Radars Chief Engineer developing advanced packaging technologies for advanced radars, electronic warfare, and communication sensors. Matt has been in the electronics industry since 1988 with most of those years in the industry developing IC packaging technologies, powertrain electronics, radar sensors and harsh environment electronics for automotive and commercial vehicles. He has 13 published papers, 8 patents and 4 defensive publications in the automotive world, and 5 patents with the Navy.
John Oakley
Semiconductor Research Corporation
Science Director
Durham, North Carolina
Presentation Title: SRC's Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap: Driving a New Era of Innovation in Semiconductors and Digital Twins
Biography: John Oakley, a Science Director at SRC, is focused on leading several collaborative research programs including Hardware Security (HWS), Packaging (PKG), AI Hardware (AIHW), and Supply Chain AI Realized Future (SCARF). John works closely with government, industry, and university partners to advance these research topics. Through this work John has created and managed research programs in collaboration with industry, government, and academia. John also serves as a Board member of the Florida Institute for Cybersecurity Research (FICS).
A graduate of Texas A&M University, John has over 20 years of successful digital design and architecture experience in industry and was formerly a RF Control Architect at Intel Corporation, at Motorola, Freescale, Fujitsu. John has 14 issued patents and has developed more than 55 successful integrated devices, several of which have shipped in high volumes. He has worked in numerous digital system spaces and was focused on the transceiver and modem fields and on the control planes of cellular platforms.