Matthew Walsh
Industrial Base Analysis and Sustainment (IBAS)
Naval Surface Warfare Center
Crane, IN
Presentation Title: OUSD IBAS RESHAPE Project
Abstract: As microelectronic technology developments occurred in the 1980s and 1990s, it was perceived that packaging technologies became very mature and did not require new developments. Therefore, the majority of microelectronics packaging manufacturing was off shored to China and Pacific Rim countries such as Singapore, Malesia, Taiwan, Hong Kong, Indonesia for their low-cost labor and the absence of environmental restrictions to manufacturing. The microelectronics packaging industry since this off-shoring has remained being seen as mature with no requirements for developments and thus remains off-shore.
With Moore's Law coming to an end for IC processing, and a continuing need to reduce SWaP-C and increase performance, the introduction of 2.5-D and 3-D Advanced Packaging has become a focal point for DoD and Commercial applications. It is now in the forefront of development activities worldwide. As the microelectronics evolution progresses, circuit feature sizes decrease to accommodate the need for high-density packaging.
Theoretical feature size limits in the 2-D space and the cost to increase wafer size forces suppliers to move towards 3-D heterogeneous architectures. Integrating ICs from multiple technology nodes to increase cost-efficiency by only fabricating the components that need the highest performance, power advantage, and area savings in the latest node technology, while fabricating other system components at cheaper nodes. Improvements in advanced packaging is required for seamless integration. Although the European and Asian semiconductor industries have embraced these developments, no single country has emerged as a front-runner in the development and scale-up of advanced microelectronics 3-D packaging technologies and manufacturing processes. This provides an opportunity for the US to advance as a worldwide leader, developer, and supplier of these foundational and dual-use technologies.
The focus of the OUSD IBAS RESHAPE (Re-shore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics) effort is to develop a domestic, trusted, pure-play and open-access advanced packaging manufacturing ecosystem for low-volume/high-mix production of 2.5-D and 3-D Advanced System Integration and Packaging (ASIP) secure solutions. This prototype effort relates to foundational Advanced Packaging manufacturing capabilities required for advanced system integration of microelectronics packages including the following:
- Wafer Preparation
- Wafer Bumping
- Silicon Interposer Fabrication
- III/V Interposer Fabrication
- Classified Interposer Assembly
- Advanced Test and Failure Analysis Capability
- Fan-Out Wafer-Level Packaging
- Wafer-Level High-Density Interconnects
- Advanced Thermal Technologies
- Specialized Packaging for RF and Photonics
- Assembly Design Kits (ADKs) for SOTA Computer-Aided Design (CAD) Tools
Biography: Matthew Walsh is the Advanced Packaging Chief Engineer, Industrial Policy, Industrial Base Analysis and Sustainment (IBAS) Program Office of the Assistant Secretary of Defense for Industrial Base Policy. He is the technical lead on the Secure Advanced Packaging project within the Reshore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics (RESHAPE) effort, and technical SME for other microelectronics projects within the OSD IBAS. Within the Navy, Matt was Advanced Radars Chief Engineer developing advanced packaging technologies for advanced radars, electronic warfare, and communication sensors. Matt has been in the electronics industry since 1988 with most of those years in the industry developing IC packaging technologies, powertrain electronics, radar sensors and harsh environment electronics for automotive and commercial vehicles. He has 13 published papers, 8 patents and 4 defensive publications in the automotive world, and 5 patents with the Navy.
John Oakley
Semiconductor Research Corporation
Science Director
Durham, North Carolina
Presentation Title: SRC's Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap: Driving a New Era of Innovation in Semiconductors and Digital Twins
Abstract:The semiconductor industry is on the brink of a new era of innovation, propelled by the convergence of Microelectronics and Advanced Packaging Technologies (MAPT). This talk explores how the Semiconductor Research Corporation (SRC) is spearheading this transformation by democratizing and accelerating innovation in research, design, and manufacturing.
Central to this initiative is the development of a Digital Twin Platform/Framework (DT backbone) that serves as the foundation for collaborative endeavors. This framework will ensure data and tool accessibility across all members while prioritizing secure management protocols. SRC is fostering an ecosystem where members can engage and exchange ideas, collaborate on project proposals, conduct privately-funded projects, access funding opportunities, and test Digital Twin innovations.
An integral aspect of SRC's MAPT Roadmap is the emphasis on attracting and training a workforce equipped to harness the potential of Digital Twins. By integrating Digital Twin technologies into education and training programs, SRC ensures a pipeline of talent capable of driving innovation forward. Ultimately, SRC's MAPT roadmap is not only about conceptualization but also about delivery. By seamlessly integrating Digital Twin innovations into the manufacturing value chain, SRC is paving the way for a future where semiconductor advancements are not only envisioned but also realized.
Biography: John Oakley, a Science Director at SRC, is focused on leading several collaborative research programs including Hardware Security (HWS), Packaging (PKG), AI Hardware (AIHW), and Supply Chain AI Realized Future (SCARF). John works closely with government, industry, and university partners to advance these research topics. Through this work John has created and managed research programs in collaboration with industry, government, and academia. John also serves as a Board member of the Florida Institute for Cybersecurity Research (FICS).
A graduate of Texas A&M University, John has over 20 years of successful digital design and architecture experience in industry and was formerly a RF Control Architect at Intel Corporation, at Motorola, Freescale, Fujitsu. John has 14 issued patents and has developed more than 55 successful integrated devices, several of which have shipped in high volumes. He has worked in numerous digital system spaces and was focused on the transceiver and modem fields and on the control planes of cellular platforms.
Art Wall
Director of Engineering & Fab Operations
NextFlex
Presentation Title: The Use of Additive Hybrid Electronics as a Key Element in the National Strategy for Advanced Packaging
Abstract: There are many challenges and opportunities for the use of additive or printed electronic interconnect to packaging. The manufacturing opportunities include significantly lower cost of entry, inherently fewer process steps, wide variety of materials options, reduced impact on waste, water and power, and the opportunity for viable low volume, high mix electronic device production. The technology is still evolving with some notable innovations that can have a large impact on the future capability. In some cases, these can be disruptive but need further maturity. In the end, reliable solutions to integrated high resolution printing and economical multilayer processes are required to have the greatest impact on electronic advanced packaging.
Biography: Art Wall is the Director of Engineering and Fab Operations at NextFlex, managing the Technology Hub which houses multiple novel electronics manufacturing capabilities for Flexible Hybrid Electronics development and prototyping, a novel new way of producing electronics devices. Prior to joining NextFlex, Art led many different groups of organizations and technologies associated with hard drive products for both IBM and Hitachi Global Storage Technologies. His most recent efforts prior to joining NextFlex were as a co-founder and Vice President of NuvoSun, an innovative thin film photovoltaic company that was acquired by The Dow Chemical Company. Art has a Ph.D. in Materials Science from the University of Minnesota, has co-authored more than 30 articles in refereed journals, presented at more than 20 US and International Conferences, and holds 7 US patents.
Dr. Radha Nagarajan
SVP and CTO
Marvell's Optical and Cloud Connectivity Group
Presentation Title: 2.5D/3D Integration for High-Speed Light Engines
Abstract: Massive deployments of AI data centers have rapidly pushed the speed of optical interconnects from 800Gbit/s to 1.6Tbit/s and beyond, while placing a premium on power, performance and latency.
In this talk, we discuss the use of 3D heterogeneous integration, on silicon photonics, to enable low energy, high density high speed optical interconnects for these applications.
Heterogeneous optical integration in this talk, is where separately manufactured electronic components and semiconductor lasers are assembled on to an active silicon photonics interposer to form a Light Engine.
This process allows for the integration of components independently designed and optimized from several different technology and foundry platforms onto a common interposer.
Biography: Dr. Radha Nagarajan is currently the Senior Vice President and Chief Technology Officer of Marvell's Optical and Cloud Connectivity Group. At Marvell, he manages the development of the company's optical platform technology and products. Concurrently, he is a Visiting Professor at the Department of Electrical and Computer Engineering at the National University of Singapore. He received his B.Eng. from the National University of Singapore, M.Eng. from the University of Tokyo, Japan and Ph.D. from the University of California, Santa Barbara, USA, all in Electrical Engineering.
Dr. Nagarajan's other recognitions include the IEEE/LEOS Aron Kressel Award, the IPRM Award and the Optica David Richardson Medal for breakthrough work in the development and manufacturing of photonic integrated circuits. He was named to Electro Optics’ The Photonics100 in 2024 which honors the industry’s most innovative people. He has been awarded more than 245 US patents and is a Fellow of Optica, IEEE, and IET.
Dr. Peter de Bock
Program Director
Advanced Research Projects Agency-Energy (ARPA-E)
US Department of Energy
Presentation Title:ARPA-E COOLERCHIPS Technology for a Future of Energy Efficient High Power Density/AI Data Centers
Abstract: The Department of Energy (DOE) Advanced Research Projects Agency – Energy (ARPA-E) was founded to support high‐risk/high‐reward technologies that could lead to transformational impact in the energy space.
The $42M COOLERCHIPS program supports teams to develop a new generation of transformational, highly efficient, and reliable cooling technologies for data centers. The target for COOLERCHIPS is to reduce total cooling energy TUE to less than 5% of a typical data center’s IT load at any time and any U.S. location for future high-density compute systems for Enterprise, AI and High-Performance Computing.
Technologies supported include broad technical teams pursuing transformational concepts in single-phase, two-phase, immersion and passive cooling methods. COOLERCHIPS technologies will achieve these goals by dramatically reducing the thermal resistance of heat rejection to R<0.01 K/W through diverse approaches, which will allow for coolants to exist at temperatures much closer to operating temperatures of the latest generation of chips (targeting <10°C difference between chip and coolant for >1kW chipsets). This will result in more efficient heat removal from the facility. The program will develop solutions for systems of >80kW/m3, equivalent to about >3kW per server or 126kW/42U rack and modular data centers with >20kW/m3 or about >1MW per 40ISO container. In addition, there is an emphasis to develops new tools and methods for component and system reliability engineering to ensure that data center system uptime similar to existing air-cooled data centers today, 99.982% tier 3 can be maintained.
An overview of the program, technology approaches and impact paths will be presented.
Biography: Dr. Peter de Bock currently serves as Program Director at the Advanced Research Projects Agency-Energy (ARPA-E) for the US Department of Energy.
At ARPA-E Dr. de Bock developed the COOLERCHIPS program focused on making a transformational leap in efficiency of cooling of Data Center and leads and developed the ASCEND and PRE-TRAILS programs to realize a future of sustainable aviation. In addition, Dr. de Bock manages projects in the areas of ultra-high power density battery systems, hydrogen storage and propulsion, additive manufacturing and power electronics. Prior to joining ARPA-E, Dr. de Bock worked at GE Research as Principal Engineer ThermoSciences and platform lead Power-Thermal Mechanical Systems. Dr. de Bock is the former chair of ASME K-16 committee on Heat Transfer in Electronics equipment, ASME Fellow, AIAA member and holds 50+ patents and publications.
Dr. de Bock received his Ph.D. in Mechanical Engineering from the University of Cincinnati and holds MSc degrees from University of Twente in the Netherlands, and University of Warwick in the United Kingdom.